Samsung’s new 2 nm foundry process to cut chip size by 17%

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The BSPDN, Samsung is set to apply for mass production for the 2 nm process from 2027, also improves performance and power efficiency by 8% and 15%, compared with the chips with the front-end power delivery networks, Lee Sungjae, vice president and Foundry PDK Development Team at Samsung.

A new contract chipmaking technology, dubbed the backside power delivery network (BSPDN), will reduce the size of a 2-nanometer chip by 17%, compared with the traditional front-end power delivery technology, said Samsung Electronics Co.'s foundry business executive on Thursday.

SF3 has improved chip performance and power efficiency by 30% and 50%, respectively, while reducing the chip size by 35%, compared with the chips produced on the first-generation GAA process, Lee added.

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Category: Economy

Markets: South Korea

Topics: Technology Process Power Samsung Chip Chips Performance Foundry Bspdn Delivery Compared

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Fact Checked: Legitimate

Article Type: News Report

Published On: 2024-08-22 @ 17:54:12 (1 hours ago)

News Timezone: GMT +8:00

News Source URL: kedglobal.com

Language: English

Article Length: 326 words

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Copyright Owner: © Korea Economic Daily

News ID: 22205881

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